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Alternative TitleA Design of Digital Delay Line Based on FPGA
刘鹏; 许可; 北京8701信箱
Source Publication微计算机信息
Keyword数字延迟线 Fpga Iodelay
Other AbstractThe design of a new digital delay line(DDL) is introduced in this paper.This DDL can achieve the time delay by the step of 0.1ns, and the delay duration can be easily expanded to more than 10ms in this scheme.The delay circuit was constituted by a wide delay unit and a narrow delay unit.The wide delay unit was build up by user-defined counters, while the narrow delay unit make up of an IODELAY unit.Its designed code has been compiled and simulated on FPGAdv software.It had been applied to control the delay of the radar signal envelop in radar altimeter simulator successfully
Funding Project中国科学院空间科学与应用研究中心
Document Type期刊论文
Corresponding Author北京8701信箱
Recommended Citation
GB/T 7714
刘鹏,许可,北京8701信箱. 一种基于FPGA的高精度大动态数字延迟单元的设计[J]. 微计算机信息,2010,26(8):132-134.
APA 刘鹏,许可,&北京8701信箱.(2010).一种基于FPGA的高精度大动态数字延迟单元的设计.微计算机信息,26(8),132-134.
MLA 刘鹏,et al."一种基于FPGA的高精度大动态数字延迟单元的设计".微计算机信息 26.8(2010):132-134.
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