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一种基于FPGA的高精度大动态数字延迟单元的设计
Alternative TitleA Design of Digital Delay Line Based on FPGA
刘鹏; 许可; 北京8701信箱
Department国家863计划微波遥感技术实验室
Source Publication微计算机信息
2010
Volume26Issue:8Pages:132-134
ISSN1008-0570
Language中文
Keyword数字延迟线 Fpga Iodelay
Abstract本文提出了一种数字延迟单元的设计方案,该方案能够实现0.1ns的延迟度精度和10ms的动态范围,通过调节该方案的工作参数可以很方便的实现更大的动态范围。该电路在Virtex5系列的FPGA上实现,其核心由粗延时单元和精延时单元两部分组成,粗延时单元采用计数器法实现,精延时单元的核心由IODELAY基元构成,语言代码通过了FPGAdv软件的综合和仿真。目前该单元电路已成功的应用在卫星雷达高度计的地面回波模拟器上。
Other AbstractThe design of a new digital delay line(DDL) is introduced in this paper.This DDL can achieve the time delay by the step of 0.1ns, and the delay duration can be easily expanded to more than 10ms in this scheme.The delay circuit was constituted by a wide delay unit and a narrow delay unit.The wide delay unit was build up by user-defined counters, while the narrow delay unit make up of an IODELAY unit.Its designed code has been compiled and simulated on FPGAdv software.It had been applied to control the delay of the radar signal envelop in radar altimeter simulator successfully
Funding Project中国科学院空间科学与应用研究中心
Document Type期刊论文
Identifierhttp://ir.nssc.ac.cn/handle/122/1866
Collection微波遥感部
Corresponding Author北京8701信箱
Recommended Citation
GB/T 7714
刘鹏,许可,北京8701信箱. 一种基于FPGA的高精度大动态数字延迟单元的设计[J]. 微计算机信息,2010,26(8):132-134.
APA 刘鹏,许可,&北京8701信箱.(2010).一种基于FPGA的高精度大动态数字延迟单元的设计.微计算机信息,26(8),132-134.
MLA 刘鹏,et al."一种基于FPGA的高精度大动态数字延迟单元的设计".微计算机信息 26.8(2010):132-134.
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