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High performance hardware architecture for sparse signal reconstruction based on systolic array
Chen, Zhenzhen; Jiang, Yuanda; Wang, Chao; Yu, Wenkai; Zheng, Fu; Sun, Zhibin; Zhai, Guangjie
Department空间技术部
Source PublicationJournal of Computational Information Systems
2014
Volume10Issue:24Pages:10611-10622
ISSN1553-9105
Language英语
AbstractCompressed sensing realizes the sub-sampling of the sparse signal but with high computational effort. For this, many hardware implementations based on Orthogonal Matching Pursuit (OMP) algorithm have been researched, avoiding the direct matrix inversion calculation by Cholesky or QR decomposition. However, the computational complexity is still high, and the reconstruction precision is poor, which is unfavorable for extension. In order to address this problem, a high performance hardware implementation was proposed in this paper which used Coordinate Rotation Digital Computer (CORDIC) method constituting a systolic array to perform QR decomposition. This hardware architecture improves systolic array module and corresponding scheduling processing module by adding delay units, and can recover an 8-sparse signal of column dimension 256 in the order of columns, with the speed nearly 13 times faster than the software. Meanwhile, since the mean square error has a boltzmann relationship with the sparsity of the signals, the hardware performs well when the sparsity is below 8. Moreover, the curve fittings for software and hardware match well further proves the reconstruction ability of this hardware architecture. Finally, based on this hardware structure, a single photon imaging system was constructed, showing that, it can significantly speed up the imaging speed.
Indexed ByEI
Document Type期刊论文
Identifierhttp://ir.nssc.ac.cn/handle/122/4400
Collection空间技术部
Corresponding AuthorJiang, Yuanda
Recommended Citation
GB/T 7714
Chen, Zhenzhen,Jiang, Yuanda,Wang, Chao,et al. High performance hardware architecture for sparse signal reconstruction based on systolic array[J]. Journal of Computational Information Systems,2014,10(24):10611-10622.
APA Chen, Zhenzhen.,Jiang, Yuanda.,Wang, Chao.,Yu, Wenkai.,Zheng, Fu.,...&Zhai, Guangjie.(2014).High performance hardware architecture for sparse signal reconstruction based on systolic array.Journal of Computational Information Systems,10(24),10611-10622.
MLA Chen, Zhenzhen,et al."High performance hardware architecture for sparse signal reconstruction based on systolic array".Journal of Computational Information Systems 10.24(2014):10611-10622.
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