NSSC OpenIR  > 保障部/保障与试验验证中心
一种暴露芯片衬底面的封装方法
Application Number

CN201510524221.3

封国强; 上官士鹏; 韩建伟; 马英起; 朱翔; 陈睿
2015-08-24
ClassificationH01l21/50(2006.01)i ; H01l21/56(2006.01)i ; H01l21/60(2006.01)i
Country中国
Abstract

本发明提供了一种暴露芯片衬底面的封装方法,该封装方法通过利用本发明所述的封装方法,能够在芯片封装过程中直接实现其衬底面的暴露处理,方便进行芯片的可靠性测试和失效分析;且能够保证芯片封装处理过程中芯片功能和结构不受影响。解决了现有的芯片处理方法,无法做到在封装的过程中打开芯片衬底面的功能。

Language中文
Document Type专利
Identifierhttp://ir.nssc.ac.cn/handle/122/5246
Collection保障部/保障与试验验证中心
Recommended Citation
GB/T 7714
封国强,上官士鹏,韩建伟,等. 一种暴露芯片衬底面的封装方法[P]. 2015-08-24.
Files in This Item: Download All
File Name/Size DocType Version Access License
2015105242213.pdf(1029KB)专利 开放获取CC BY-NC-SAView Download
Related Services
Recommend this item
Bookmark
Usage statistics
Export to Endnote
Google Scholar
Similar articles in Google Scholar
[封国强]'s Articles
[上官士鹏]'s Articles
[韩建伟]'s Articles
Baidu academic
Similar articles in Baidu academic
[封国强]'s Articles
[上官士鹏]'s Articles
[韩建伟]'s Articles
Bing Scholar
Similar articles in Bing Scholar
[封国强]'s Articles
[上官士鹏]'s Articles
[韩建伟]'s Articles
Terms of Use
No data!
Social Bookmark/Share
File name: 2015105242213.pdf
Format: Adobe PDF
All comments (0)
No comment.
 

Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.