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An optimal space-borne Solid-State Recorder based on domestic chips
Li, S.; Song, Q.; Song, J.W.; Wang, W.; Zhu, Y.; An, J.S.
Source PublicationMechatronics Engineering and Electrical Engineering - Proceedings of the 2014 International Conference on Mechatronics Engineering and Electrical Engineering, CMEEE 2014
2015
Pages83-86
Language英语
ISBN9781138027190
AbstractThis article describes the design and implementation of a novel space-borne Solid-State Recorder (SSR) by domestic chips which have never been used in space environment. Currently, the foreign high-grade chips embargo seriously restricted the development of China’s space cause. The attempt of domestic chips in this field will change the situation. The domestic chips include a radiation hardened CPU and three types of 3D package radiation-hardened memory chips. The structure of novel SSR is CPU + FPGA + main storage area. The main storage area, which has the capacity of 512 GB, is made of eight pieces of 64 GB NAND FLASH. FPGA and CPU are connected by a PCI bus, which increase the speed of commands and state signal. The SSR is designed for a satellite and the system cascade tests with 19 payloads are finished. Its throughput is 300 Mbps and can be raised to 1 Gbps and the power is no more than 5.4 W. Its capacity can be expanded to TB by PCI. The result shows that the SSR meets the requirements of practical application and the performance of which can compete with imported components. © 2015 Taylor & Francis Group, London.
Conference NameInternational Conference on Mechatronics Engineering and Electrical Engineering, CMEEE 2014
Conference DateOctober 17, 2014 - October 19, 2014
Conference PlaceSanya, Hainan, China
Indexed ByEI
Document Type会议论文
Identifierhttp://ir.nssc.ac.cn/handle/122/5406
Collection空间技术部
Affiliation空间技术部
Recommended Citation
GB/T 7714
Li, S.,Song, Q.,Song, J.W.,et al. An optimal space-borne Solid-State Recorder based on domestic chips[C]:CRC Press/Balkema,2015:83-86.
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