| 锁相环频率合成器最优环路带宽的选取 | |
| Alternative Title | Selection of the Optimum Loop Bandwidth of PLL Frequency Synthesizer |
| 孙家星; 孙越强; 杜起飞 | |
| Department | 空间环境部 |
| Source Publication | 固体电子学研究与进展
 |
| 2016 | |
| Volume | 36Issue:6Pages:457 |
| ISSN | 1000-3819 |
| Language | 中文 |
| Keyword | 锁相环 频率合成器 环路带宽 相位噪声 |
| Abstract | 锁相环频率合成器环路带宽值的选取直接影响其输出相位噪声。基于此,本文首先介绍了锁相环的基本组成部分,然后分析了晶振、集成锁相芯片和压控振荡器相位噪声对频率合成器环路输出端的噪声影响,从而导出了最优环路带宽计算公式。并且通过基于PE3236芯片的频率合成器的输出相位噪声测量对最优环路带宽公式正确性进行了验证。结果表明:当根据最优环路带宽公式取值时,锁相环频率合成器的输出相位噪声满足实际应用需求。 |
| Other Abstract | The selection of bandwidth value of PLL frequency synthesizer has a direct effect on the output phase noise. Base on this, the basic components of the PLL was firstly introduced, and then the influence of the crystal oscillator, integrated PLL chip and the phase noise of the voltage controlled oscillator on the noise at the output of the frequency synthesizer loop were analyzed in the paper. As a result, a formula for calculating the optimal loop bandwidth was derived. And the accuracy of the formula was verified by the measurement of the output phase noise of the frequency synthesizer based on the PE3236 chip. The results show that when the optimal bandwidth value is selected according to the formula, the output phase noise of PLL frequency synthesizer meet the needs of practical application. |
| Indexed By | CSCD |
| Citation statistics | |
| Document Type | 期刊论文 |
| Identifier | http://ir.nssc.ac.cn/handle/122/5739 |
| Collection | 空间环境部 |
| Recommended Citation GB/T 7714 | 孙家星,孙越强,杜起飞. 锁相环频率合成器最优环路带宽的选取[J]. 固体电子学研究与进展,2016,36(6):457. |
| APA | 孙家星,孙越强,&杜起飞.(2016).锁相环频率合成器最优环路带宽的选取.固体电子学研究与进展,36(6),457. |
| MLA | 孙家星,et al."锁相环频率合成器最优环路带宽的选取".固体电子学研究与进展 36.6(2016):457. |
| Files in This Item: | ||||||
| File Name/Size | DocType | Version | Access | License | ||
| 2016366457.pdf（623KB） | 期刊论文 | 作者接受稿 | 开放获取 | CC BY-NC-SA | Application Full Text | |
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