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Alternative TitleSelection of the Optimum Loop Bandwidth of PLL Frequency Synthesizer
孙家星; 孙越强; 杜起飞
Source Publication固体电子学研究与进展
Keyword锁相环 频率合成器 环路带宽 相位噪声
Other AbstractThe selection of bandwidth value of PLL frequency synthesizer has a direct effect on the output phase noise. Base on this, the basic components of the PLL was firstly introduced, and then the influence of the crystal oscillator, integrated PLL chip and the phase noise of the voltage controlled oscillator on the noise at the output of the frequency synthesizer loop were analyzed in the paper. As a result, a formula for calculating the optimal loop bandwidth was derived. And the accuracy of the formula was verified by the measurement of the output phase noise of the frequency synthesizer based on the PE3236 chip. The results show that when the optimal bandwidth value is selected according to the formula, the output phase noise of PLL frequency synthesizer meet the needs of practical application.
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GB/T 7714
孙家星,孙越强,杜起飞. 锁相环频率合成器最优环路带宽的选取[J]. 固体电子学研究与进展,2016,36(6):457.
APA 孙家星,孙越强,&杜起飞.(2016).锁相环频率合成器最优环路带宽的选取.固体电子学研究与进展,36(6),457.
MLA 孙家星,et al."锁相环频率合成器最优环路带宽的选取".固体电子学研究与进展 36.6(2016):457.
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