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A single event upset hardened flip-flop design utilizing layout technique
Wang, Haibin1; Chu, Jiamin1; Wei, Jinghe2; Shi, Junwei3; Sun, Hongwen1; Han, Jianwei4; Qian, Rong5
Department空间技术部
Source PublicationMicroelectronics Reliability
2019
Volume102
DOI10.1016/j.microrel.2019.113496
ISSN0026-2714
Language英语
AbstractA novel Quatro-based flip-flop design with low penalty was proposed. By utilizing layout technique, SEU hardness was achieved in this design because of charge sharing between the introduced PMOS transistors. Both the proposed design and the reference flip-flop were fabricated in a 65 nm standard CMOS technology. The pulsed laser experiment results demonstrate that the new design has a larger upset threshold and lower SEU error rate compared with the reference. The area and delay penalties are not significant, i.e., 13% and 37%, respectively. © 2019 Elsevier Ltd
Indexed ByEI
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Cited Times:1[WOS]   [WOS Record]     [Related Records in WOS]
Document Type期刊论文
Identifierhttp://ir.nssc.ac.cn/handle/122/7179
Collection空间技术部
Affiliation1.College of IoT Engineering, Hohai University, Changzhou; Jiangsu; 213022, China;
2.No.58 Research Institute, China Electronics Technology Group Corporation, Wuxi; Jiangsu; 214035, China;
3.Changzhou Taiping Communication Technology Co. Ltd, Changzhou; Jiangsu; 213022, China;
4.National Space Science Center, Beijing; 101499, China;
5.Jiangsu Jotry Electrical Technology Co. Ltd, Changzhou; Jiangsu; 213100, China
Recommended Citation
GB/T 7714
Wang, Haibin,Chu, Jiamin,Wei, Jinghe,et al. A single event upset hardened flip-flop design utilizing layout technique[J]. Microelectronics Reliability,2019,102.
APA Wang, Haibin.,Chu, Jiamin.,Wei, Jinghe.,Shi, Junwei.,Sun, Hongwen.,...&Qian, Rong.(2019).A single event upset hardened flip-flop design utilizing layout technique.Microelectronics Reliability,102.
MLA Wang, Haibin,et al."A single event upset hardened flip-flop design utilizing layout technique".Microelectronics Reliability 102(2019).
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