NSSC OpenIR  > 空间技术部
SpaceWire Codec接收端FPGA时序设
Alternative TitleTiming design of SpaceWire Codec receiver based on FPGA
唐萍; 李慧军; 北京8701信箱
Department空间综合电子技术研究室
Source Publication微计算机信息
2009
Volume25Issue:2Pages:178-179,198
ISSN1008-0570
Language中文
KeywordFpga Spacewire Codec 复位 Ds解码 多时钟域设计
AbstractSpaceWire是一种面向空间应用的数据总线网络,它支持高速、点对点、全双工的串行总线传输。本文实现了基于FPGA的SpaceWire Codec接收端实现过程中时钟的恢复,复位信号的处理,DS信号的检测和处理,介绍了多时钟域的设计方法。
Other AbstractSpaceWire is a full-duplex, bidirectional, serial, point-to-point data link for on-board processing applications. A design and realization scheme of SpaceWire Codec receiver based on FPGA is presented in this paper, which includes clock recovery, reset signal processing, DS signal detection and processing as well as design methods in multi-asynchronous clock designs.
Funding Project中国科学院空间科学与应用研究中心
Document Type期刊论文
Identifierhttp://ir.nssc.ac.cn/handle/122/765
Collection空间技术部
Corresponding Author北京8701信箱
Recommended Citation
GB/T 7714
唐萍,李慧军,北京8701信箱. SpaceWire Codec接收端FPGA时序设[J]. 微计算机信息,2009,25(2):178-179,198.
APA 唐萍,李慧军,&北京8701信箱.(2009).SpaceWire Codec接收端FPGA时序设.微计算机信息,25(2),178-179,198.
MLA 唐萍,et al."SpaceWire Codec接收端FPGA时序设".微计算机信息 25.2(2009):178-179,198.
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