NSSC OpenIR  > 空间技术部
SpaceWire总线接口终端的设计与实现
Alternative TitleThe Design and Realization of SpaceWire Interface Terminal
陈健飞; 曹松; 北京8701信箱
Department空间综合电子技术研究室
Source Publication微计算机信息
2010
Volume26Issue:23Pages:123-124,199
ISSN1008-0570
Language中文
KeywordSpacewire Cpu 双口ram Fpga 存储器
AbstractSpaceWire是面向航天应用的高速串行总线协议,本文介绍了SpaceWire总线接口终端的硬件设计方案、FPGA设计、仿真验证及电路测试结果。
Other AbstractSpaceWire is a high-speed serial bus protocol for aerospace applications.This article describes the SpaceWire bus terminal s hardware design, FPGA design, results of simulation and circuit tests.
Funding Project中国科学院空间科学与应用研究中心
Document Type期刊论文
Identifierhttp://ir.nssc.ac.cn/handle/122/766
Collection空间技术部
Corresponding Author北京8701信箱
Recommended Citation
GB/T 7714
陈健飞,曹松,北京8701信箱. SpaceWire总线接口终端的设计与实现[J]. 微计算机信息,2010,26(23):123-124,199.
APA 陈健飞,曹松,&北京8701信箱.(2010).SpaceWire总线接口终端的设计与实现.微计算机信息,26(23),123-124,199.
MLA 陈健飞,et al."SpaceWire总线接口终端的设计与实现".微计算机信息 26.23(2010):123-124,199.
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