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Study on the single-event upset sensitivity of 65-nm CMOS sequential logic circuit
Alternative TitleWOS:000546314300009;20202308792395
Li, Sai1; Han, Jianwei; Chen, Rui; Shangguan, Shipeng1; Ma, Yingqi; Wang, Xuan1
Source PublicationIEICE ELECTRONICS EXPRESS
2020
Volume17Issue:10Pages:20200102
DOI10.1587/elex.17.20200102
ISSN1349-2543
Language英语
Keywordpulsed laser single-event-upset (SEU) voltage frequency circuit architecture SOFT ERROR RATES SEU IMPACT BULK
AbstractThis study uses a pulsed laser to investigate the sensitivity of a sequential logic circuit to a Single-Event-Upset (SEU) under different supply voltages, clock frequencies, and circuit architectures. The experimented sequential logic circuit is a D flip-flop chain manufactured in 65-nm bulk CMOS technology. The results indicate that as the voltage decreases, the SEU sensibility of the circuit increases, and in particular at low voltage ranges, it increases significantly. Additionally, the effect of clock frequency on the sensitivity of the sequential logic circuit is mainly related to the propagation of Single-Event-Transients (SETs) that are generated in combinational logic circuits. It was also found that, the Set-architecture circuit is more sensitive to SEUs during the data 0 test, while the Reset-architecture circuit is more sensitive to SEUs during the data 1 test. In addition, the failure mechanisms of SEU induced by Set-structure and Reset-structure are revealed using SPICE simulations.
Indexed BySCI ; EI
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Document Type期刊论文
Identifierhttp://ir.nssc.ac.cn/handle/122/7721
Collection中国科学院国家空间科学中心
Affiliation1.Chinese Acad Sci, Natl Space Sci Ctr, Beijing 100190, Peoples R China
2.Univ Chinese Acad Sci, Beijing 100049, Peoples R China
Recommended Citation
GB/T 7714
Li, Sai,Han, Jianwei,Chen, Rui,et al. Study on the single-event upset sensitivity of 65-nm CMOS sequential logic circuit[J]. IEICE ELECTRONICS EXPRESS,2020,17(10):20200102.
APA Li, Sai,Han, Jianwei,Chen, Rui,Shangguan, Shipeng,Ma, Yingqi,&Wang, Xuan.(2020).Study on the single-event upset sensitivity of 65-nm CMOS sequential logic circuit.IEICE ELECTRONICS EXPRESS,17(10),20200102.
MLA Li, Sai,et al."Study on the single-event upset sensitivity of 65-nm CMOS sequential logic circuit".IEICE ELECTRONICS EXPRESS 17.10(2020):20200102.
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