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实现FPGA回读功能的可重构系统设计
Alternative TitleDesign of Reconfigurable System with FPGA Readback Function
周盛雨; 孙辉先; 陈晓敏; 安军社; 张健; 北京8701信箱
Department空间综合电子技术研究室
Source Publication计算机工程
2007
Volume33Issue:12Pages:270-271,274
ISSN1000-3428
Language中文
Keyword可重构 Fpga Selectmap Cpld 回读 Virtex
AbstractXilinx Virtex系列FPGA具有配置逻辑可重构、配置数据可回读的特点,该文设计了基于Virtex FPGA的一种可重构系统.FPGA采用SelectMAP配置方式,在CPU和CPLD控制下实现了配置数据加载和回读的功能.给出了系统配置FPGA和回读其配置数据的流程及相应的波形图.
Other AbstractAs FPGA is reconfigurable in logic and can be readback in data, this paper designs a reconfigurable system based on Xilinx VirtexTM FPGA. CPU and CPLD are used to configure FPGA which selects a SelectMAP configuration mode and readback configuration data in it. The paper introduces the process of the system to implement the configuration and readback function. Part of the results are shown in wave charts.
Indexed ByCSCD
Funding Project中国科学院空间科学与应用研究中心
Citation statistics
Document Type期刊论文
Identifierhttp://ir.nssc.ac.cn/handle/122/795
Collection空间技术部
Corresponding Author北京8701信箱
Recommended Citation
GB/T 7714
周盛雨,孙辉先,陈晓敏,等. 实现FPGA回读功能的可重构系统设计[J]. 计算机工程,2007,33(12):270-271,274.
APA 周盛雨,孙辉先,陈晓敏,安军社,张健,&北京8701信箱.(2007).实现FPGA回读功能的可重构系统设计.计算机工程,33(12),270-271,274.
MLA 周盛雨,et al."实现FPGA回读功能的可重构系统设计".计算机工程 33.12(2007):270-271,274.
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